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M48T59 M48T59Y, M48T59V
5.0 or 3.3 V, 64 Kbit (8 Kbit x 8) TIMEKEEPER(R) SRAM
Not For New Design
Features

Integrated ultra low power SRAM, real-time clock, power-fail control circuit, and battery Frequency test output for real-time clock software calibration Automatic power-fail chip deselect and WRITE protection WRITE protect voltages (VPFD = Power-fail deselect voltage): - M48T59: VCC = 4.75 to 5.5 V 4.5 V VPFD 4.75 V - M48T59Y: VCC = 4.5 to 5.5 V 4.2 V VPFD 4.5 V - M48T59V(a): VCC = 3.0 to 3.6 V 2.7 V VPFD 3.0 V Self-contained battery and crystal in the CAPHATTM DIP package Packaging includes a 28-lead SOIC and SNAPHAT(R) top (to be ordered separately)
28 1
PCDIP28 (PC) battery/crystal CAPHAT

SOIC package provides direct connection for a SNAPHAT top which contains the battery and crystal Microprocessor power-on reset (valid even during battery back-up mode) Programmable alarm output active in the battery back-up mode Battery low flag RoHS compliant - Lead-free second level interconnect

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SNAPHAT (SH) battery/crystal
28 1
SOH28 (MH)
a. Contact local ST sales office for availability of 3.3 V version.
April 2008
Rev 7
1/32
www.st.com 1
This is information on a product still in production but not recommended for new designs.
Contents
M48T59, M48T59Y, M48T59V
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 2.3 Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
Clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Setting the alarm clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Programmable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Battery low flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 19
4 5
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t(s uc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Maximum ratings . rod P DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ete mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 ol Package
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Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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M48T59, M48T59Y, M48T59V
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Read mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Alarm repeat mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 PCDIP28 - 28-pin plastic DIP, battery CAPHAT, package mechanical data . . . . . . . . . . . 25 SOH28 - 28-lead plastic small outline, battery SNAPHAT, pack. mech. data . . . . . . . . . . 26 SH - 4-pin SNAPHAT housing for 48mAh battery & crystal, package mech. data. . . . . . . 27 SH - 4-pin SNAPHAT housing for 120mAh battery & crystal, package mech. data. . . . . . 28 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SNAPHAT battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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List of figures
M48T59, M48T59Y, M48T59V
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 28-pin SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PCDIP28 CAPHAT connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Read mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write enable controlled, write mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chip enable controlled, write mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Back-up mode alarm waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PCDIP28 - 28-pin plastic DIP, battery CAPHAT, package outline . . . . . . . . . . . . . . . . . . . 25 SOH28 - 28-lead plastic small outline, battery SNAPHAT, package outline . . . . . . . . . . . 26 SH - 4-pin SNAPHAT housing for 48mAh battery & crystal, package outline . . . . . . . . . . 27 SH - 4-pin SNAPHAT housing for 120mAh battery & crystal, package outline . . . . . . . . . 28
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M48T59, M48T59Y, M48T59V
Description
1
Description
The M48T59/Y/V TIMEKEEPER(R) RAM is an 8 Kb x 8 non-volatile static RAM and real-time clock. The monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory and real-time clock solution. The M48T59/Y/V is a non-volatile pin and function equivalent to any JEDEC standard 8 Kb x8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special write timing or limitations on the number of writes that can be performed. The 28-pin, 600 mil DIP CAPHATTM houses the M48T59/Y/V silicon with a quartz crystal and a long life lithium button cell in a single package. The 28-pin, 330 mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT(R) housing containing the battery and crystal. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is "M4T28-BR12SH1" or "M4T32-BR12SHx" (see Table 19 on page 30).
Caution:
Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the lithium button-cell battery. Figure 1. Logic diagram
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DQ0-DQ7 M48T59 M48T59Y M48T59V
IRQ/FT RST
VSS
AI01380E
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Description Table 1.
A0-A12 DQ0-DQ7 IRQ/FT RST E G W VCC VSS
M48T59, M48T59Y, M48T59V Signal names
Address inputs Data inputs / outputs Interrupt / frequency test output (open drain) Reset output (open drain) Chip enable Output enable Write enable Supply voltage Ground
Figure 2.
28-pin SOIC connections
RST A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 28 1 2 27 3 26 4 25 5 24 6 23 7 M48T59Y 22 8 M48T59V 21 9 20 10 19 11 18 12 17 13 16 14 15 VCC W IRQ/FT A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
Figure 3.
PCDIP28 CAPHAT connections
RST A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 28 2 27 3 26 4 25 5 24 6 23 7 M48T59 22 8 M48T59Y 21 9 20 10 19 11 18 12 17 13 16 14 15
AI01381D
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VCC W IRQ/FT A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
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M48T59, M48T59Y, M48T59V Figure 4. Block diagram
IRQ/FT
Description
OSCILLATOR AND CLOCK CHAIN 32,768 Hz CRYSTAL POWER
16 x 8 BiPORT SRAM ARRAY
A0-A12
8176 x 8 SRAM ARRAY LITHIUM CELL VOLTAGE SENSE AND SWITCHING CIRCUITRY VPFD
DQ0-DQ7
E W G
VCC
RST
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Operation modes
M48T59, M48T59Y, M48T59V
2
Operation modes
As Figure 4 on page 7 shows, the static memory array and the quartz-controlled clock oscillator of the M48T59/Y/V are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible BYTEWIDETM clock information in the bytes with addresses 1FF8h-1FFFh. The clock locations contain the century, year, month, date, day, hour, minute, and second in 24 hour BCD format (except for the century). Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically. Byte 1FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BiPORTTM READ/WRITE memory cells. The M48T59/Y/V includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The M48T59/Y/V also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V/3.3 V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below the Battery Back-up Switchover Voltage (VSO), the control circuitry connects the battery which maintains data and clock operation until valid power returns. Table 2.
Mode Deselect WRITE READ READ Deselect Deselect
Operating modes
VCC 4.75 to 5.5 V or 4.5 to 5.5 V or 3.0 to 3.6 V E
VSO to VPFD
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X = VIH or VIL; VSO = Battery back-up switchover voltage.
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DQ7-DQ0 High Z DIN DOUT High Z High Z High Z
Power Standby Active Active Active CMOS standby Battery back-up mode
Read mode
The M48T59/Y/V is in the READ Mode whenever W (WRITE Enable) is high and E (Chip Enable) is low. The unique address specified by the 13 address inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the Chip Enable Access time (tELQV) or Output Enable Access time (tGLQV).
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M48T59, M48T59Y, M48T59V
Operation modes
The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain active, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access. Figure 5. Read mode AC waveforms
tAVAV A0-A12 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 VALID tGHQZ VALID tAXQX tEHQZ
Note: Table 3.
WRITE enable (W) = High. Read mode AC characteristics
Parameter(1)
Symbol
tAVAV tAVQV(2) tELQV(2) tGLQV(2) tELQX(3) tGLQX(3) tEHQZ(3) tGHQZ(3) tAXQX(2)
READ cycle time
Address valid to output valid
Chip enable low to output valid
Output enable low to output valid
Chip enable low to output transition Output enable low to output transition Chip enable high to output Hi-Z Output enable high to output Hi-Z Address transition to output transition
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AI01385
M48T59/Y/V Unit
ns 70 70 35 ns ns ns ns ns 25 25 ns ns ns
5 5
10
1. Valid for ambient operating temperature: TA = 0 to 70C; VCC = 4.5 to 5.5 V, 4.75 to 5.5 V, or 3.0 to 3.6 V (except where noted). 2. CL = 100pF (see Figure 13 on page 22). 3. CL = 5pF (see Figure 13 on page 22).
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Operation modes
M48T59, M48T59Y, M48T59V
2.2
Write mode
The M48T59/Y/V is in the WRITE Mode whenever W and E are low. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from WRITE Enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; however, if the output bus has been activated by a low on E and G a low on W will disable the outputs tWLQZ after W falls.
Figure 6.
Write enable controlled, write mode AC waveforms
tAVAV A0-A12 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHAX
DQ0-DQ7
Figure 7.
Chip enable controlled, write mode AC waveforms
A0-A12
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tELEH
tEHAX
tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI01387B
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M48T59, M48T59Y, M48T59V Table 4. Write mode AC characteristics
Operation modes
M48T59/Y/V Symbol Parameter(1) Min tAVAV tAVWL tAVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ(2)(3) tAVWH tAVEH tWHQX
(2)(3)
-70 Max
Unit
WRITE cycle time Address valid to WRITE enable low Address valid to chip enable low WRITE enable pulse width Chip enable low to chip enable high WRITE enable high to address transition Chip enable high to address transition Input valid to WRITE enable high Input valid to chip enable high WRITE enable high to input transition Chip enable high to input transition WRITE enable low to output Hi-Z Address valid to WRITE enable high Address valid to chip enable high WRITE enable high to output transition
70 0 0 50 55 0 0 30 30 5 5
ns ns ns ns ns ns ns ns ns
60
1. Valid for ambient operating temperature: TA = 0 to 70C; VCC = 4.5 to 5.5 V, 4.75 to 5.5 V, or 3.0 to 3.6 V (except where noted). 2. CL = 5pF (see Figure 13 on page 22).
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Data retention mode
With valid VCC applied, the M48T59/Y/V operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs become high impedance, and all inputs are treated as "don't care." Note:
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A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48T59/Y/V may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery which preserves data and powers the clock. The internal button cell will maintain data in the M48T59/Y/V for an accumulated period of at least 7 years when VCC is less than VSO. As system power returns and VCC rises above VSO, the battery is disconnected and the power supply is switched to external VCC. Deselect continues for trec after VCC reaches VPFD (max). For more information on Battery Storage Life refer to the Application Note AN1012.
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Clock operations
M48T59, M48T59Y, M48T59V
3
3.1
Clock operations
Reading the clock
Updates to the TIMEKEEPER(R) registers should be halted before clock data is read to prevent reading data in transition. The BiPORTTM TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ Bit, D6 in the Control register (1FF8h). As long as a '1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating is within a second after the bit is reset to a '0.'
3.2
Setting the clock
Bit D7 of the Control register (1FF8h) is the WRITE Bit. Setting the WRITE Bit to a '1,' like the READ Bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24 hour BCD format (see Table 5 on page 13). Resetting the WRITE Bit to a '0' then transfers the values of all time registers (1FF9h1FFFh) to the actual TIMEKEEPER counters and allows normal operation to resume. After the WRITE Bit is reset, the next clock update will occur within approximately one second. See the Application Note AN923, "TIMEKEEPER Rolling Into the 21st Century" for information on Century Rollover. Note: Upon power-up following a power failure, both the WRITE Bit and the READ Bit will be reset to '0.'
3.3
Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP Bit is the MSB of the seconds register. Setting it to a '1' stops the oscillator. The M48T59/Y/V in the DIP package is shipped from STMicroelectronics with the STOP Bit set to a '1.' When reset to a '0,' the M48T59/Y/V oscillator starts within one second.
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It is not necessary to set the WRITE Bit when setting or resetting the FREQUENCY TEST Bit (FT), the STOP Bit (ST) or the CENTURY ENABLE Bit (CEB).
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M48T59, M48T59Y, M48T59V Table 5.
Address D7 1FFFh 1FFEh 1FFDh 1FFCh 1FFBh 1FFAh 1FF9h 1FF8h 1FF7h 1FF6h 1FF5h 1FF4h 1FF3h 1FF2h 1FF1h 1FF0h 0 0 0 0 0 ST W WDS AFE RPT4 RPT3 RPT2 RPT1 Y WDF R D6 D5 D4 D3 D2 Year 10 M Month Date 0 Day Hours Minutes Seconds Calibration D1 D0 10 Years 0 0 FT 0 0
Clock operations
Register map
Data Function/range BCD format Year Month Date Century/day Hours Minutes Seconds Control Watchdog Interrupts Alarm date Alarm hours 00-99 01-12 01-31 00-01/01-07 00-23 00-59 00-59
10 date CEB CB
10 hours 10 minutes 10 seconds S
BMB BMB BMB BMB BMB RB1 RB0 4 3 2 1 0 Y Y Y ABE Y Y Y Y Y
Al. 10 date Al. 10 hours
Alarm date Alarm hours Alarm minutes Alarm seconds Y Z Y Z Y Z Y Z
Alarm 10 minutes Alarm 10 seconds Y AF Y Z Y BL
Alarm minutes
Alarm seconds
Keys: S = Sign bit FT = Frequency test bit R = Read bit W = Write bit ST = Stop bit
0 = Must be set to '0'
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Z = '0' and are read only
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01-31 00-23 00-59 00-59
AF = Alarm flag (read only) BL = Battery low (read only) WDS = Watchdog steering bit BMB0-BMB4 = Watchdog multiplier bits RB0-RB1 = Watchdog resolution bits AFE = Alarm flag enable ABE = Alarm in battery back-up mode enable RPT1-RPT4 = Alarm repeat mode bits WDF = Watchdog flag (read only) CEB = Century enable bit CB = Century bit
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Clock operations
M48T59, M48T59Y, M48T59V
3.4
Calibrating the clock
The M48T59/Y/V is driven by a quartz-controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not to exceed 35 PPM (parts per million) oscillator frequency error at 25C, which equates to about 1.53 minutes per month. With the calibration bits properly set, the accuracy of each M48T59/Y/V improves to better than +1/- 2 PPM at 25C. The oscillation rate of any crystal changes with temperature (see Figure 8 on page 15). Most clock chips compensate for crystal frequency and temperature shift error with cumbersome "trim" capacitors. The M48T59/Y/V design, however, employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 9 on page 15. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five-bit Calibration byte found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration Byte occupies the five lower order bits (D4-D0) in the Control register (1FF8h). These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is the Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles; for every 125,829,120 actual oscillator cycles, that is +4.068 or -2.034 PPM of adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768 Hz, each of the 31 increments in the Calibration Byte would represent +10.7 or -5.35 seconds per month which corresponds to a total range of +5.5 or -2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M48T59/Y/V may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. All the designer has to do is provide a simple utility that accesses the Calibration Byte. The second approach is better suited to a manufacturing environment, and involves the use of the IRQ/FT pin. The pin will toggle at 512 Hz when the Stop Bit (D7 of 1FF9h) is '0,' the FT Bit (D6 of 1FFCh) is '1,' the AFE Bit (D7 of 1FF6h) is '0,' and the Watchdog Steering Bit (D7 of 1FF7h) is '1' or the Watchdog Register is reset (1FF7h = 0). Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 PPM oscillator frequency error, requiring a -10 (WR001010) to be loaded into the Calibration Byte for correction. Note that setting or changing the Calibration Byte does not affect the Frequency Test output frequency.
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The IRQ/FT pin is an open drain output which requires a pull-up resistor for proper operation. A 500 - 10 k resistor is recommended in order to control the rise time. The FT Bit is cleared on power-down. For more information on calibration, see Application Note AN934, "TIMEKEEPER Calibration."
14/32
M48T59, M48T59Y, M48T59V Figure 8. Crystal accuracy across temperature
Frequency (ppm) 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -40 -30 -20 -10 0 10 20 30 40 50 60 F
2 = -0.038 ppm (T - T0) 10% C2
Clock operations
T0 = 25 C
Temperature C
Figure 9.
Clock calibration
NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
3.5
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AI00999
AI00594B
Registers 1FF5h-1FF2h contain the alarm settings. The alarm can be configured to go off at a prescribed time on a specific day of the month or repeat every month, day, hour, minute, or second. It can also be programmed to go off while the M48T59/Y/V is in the battery back-up mode of operation to serve as a system wake-up call. Bits RPT1-RPT4 put the alarm in the repeat mode of operation. Table 6 on page 16 shows the possible configurations. Codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. User must transition address (or toggle chip enable) to see Flag Bit change. When the clock information matches the alarm clock settings based on the match criteria defined by RPT1-RPT4, AF (Alarm Flag) is set. If AFE (Alarm Flag Enable) is also set, the
15/32
Clock operations
M48T59, M48T59Y, M48T59V
alarm condition activates the IRQ/FT pin. To disable the alarm, write '0' to the Alarm Date Register and RPT1-4. The Alarm Flag and the IRQ/FT output are cleared by a READ to the Flags Register as shown in Figure 10 on page 16. A subsequent READ of the Flags Register is necessary to see that the value of the Alarm Flag has been reset to '0.' The IRQ/FT pin can also be activated in the battery back-up mode. The IRQ/FT will go low if an alarm occurs and both the ABE (Alarm in Battery Back-up Mode Enable) and the AFE are set. The ABE and AFE bits are reset during power-up, therefore an alarm generated during power-up will only set AF. The user can read the Flag Register at system boot-up to determine if an alarm was generated while the M48T59/Y/V was in the deselect mode during power-down. Figure 11 on page 17 illustrates the back-up mode alarm timing. Figure 10. Alarm interrupt reset waveform
15ns Min A0-A12 ADDRESS 1FF0h
ACTIVE FLAG BIT
IRQ/FT
Table 6.
RPT4 1 1 1 1 0
Alarm repeat mode
RPT3 1 1 1 0 0 RPT2 1 1
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Alarm activated
Once per second Once per minute Once per hour Once per day Once per month
16/32
M48T59, M48T59Y, M48T59V Figure 11. Back-up mode alarm waveforms
trec VCC VPFD (max) VPFD (min) VSO
Clock operations
ABE, AFE bit in Interrupt Register
AF bit in Flags Register
IRQ/FT HIGH-Z HIGH-Z
3.6
Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the eight-bit Watchdog Register (Address 1FF7h). The five bits (BMB4-BMB0) that store a binary multiplier and the two lower order bits (RB1-RB0) select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (For example: writing 00001110 in the Watchdog Register = 3 x 1 or 3 seconds). Note: Accuracy of timer is within the selected resolution. If the processor does not reset the timer within the specified period, the M48T59/Y/V sets the WDF (Watchdog Flag) and generates a watchdog interrupt or a microprocessor reset. WDF is reset by reading the Flags Register (Address 1FF0h). Note:
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User must transition address (or toggle chip enable) to see Flag Bit change.
The most significant bit of the Watchdog Register is the Watchdog Steering Bit. When set to a '0,' the watchdog will activate the IRQ/FT pin when timed-out. When WDS is set to a '1,' the watchdog will output a negative pulse on the RST pin for a duration of trec. The Watchdog Register, the FT Bit, and the AFE and ABE Bits will reset to a '0' at the end of a watchdog time-out when the WDS bit is set to a '1.' The watchdog timer resets when the microprocessor performs a re-write of the Watchdog Register. The time-out period then starts over. The watchdog timer is disabled by writing a value of 00000000 to the eight bits in the Watchdog Register. The watchdog function is automatically disabled upon power-down and the Watchdog Register is cleared. If the watchdog function is set to output to the IRQ/FT pin and the frequency test function is activated, the watchdog or alarm function prevails and the frequency test function is denied.
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Clock operations
M48T59, M48T59Y, M48T59V
3.7
Power-on reset
The M48T59/Y/V continuously monitors VCC. When VCC falls to the power fail detect trip point, the RST pulls low (open drain) and remains low on power-up for trec after VCC passes VPFD (max). RST is valid for all VCC conditions. The RST pin is an open drain output and an appropriate resistor to VCC should be chosen to control rise time.
3.8
Programmable interrupts
The M48T59/Y/V provides two programmable interrupts; an alarm and a watchdog. When an interrupt condition occurs, the M48T59/Y/V sets the appropriate flag bit in the Flag Register 1FF0h. The interrupt enable bits in (AFE and ABE) in 1FF6h and the Watchdog Steering (WDS) Bit in 1FF7h allow the interrupt to activate the IRQ/FT pin. The Alarm flag and the IRQ/FT output are cleared by a READ to the Flags Register. An interrupt condition reset will not occur unless the addresses are stable at the flag location for at least 15ns while the device is in the READ Mode as shown in Figure 10 on page 16. The IRQ/FT pin is an open drain output and requires a pull-up resistor (10 k recommended) to VCC. The pin remains in the high impedance state unless an interrupt occurs or the Frequency Test Mode is enabled.
3.9
Battery low flag
The M48T59/Y/V automatically performs periodic battery voltage monitoring upon power-up and at factory-programmed time intervals of 24 hours (at day rollover) as long as the device is powered and the oscillator is running. The Battery Low Flag (BL), Bit D4 of the Flags Register 1FF0h, will be asserted high if the internal or SNAPHAT(R) battery is found to be less than approximately 2.5 V. The BL Flag will remain active until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. If a battery low is generated during a power-up sequence, this indicates that the battery voltage is below 2.5 V (approximately), which may be insufficient to maintain data integrity. Data should be considered suspect and verified as correct. A fresh battery should be installed. If a battery low indication is generated during the 24-hour interval check, this indicates the battery is near end of life. However, data has not been compromised due to the fact that a nominal VCC is supplied. In order to insure data integrity during subsequent periods of battery back-up mode, it is recommended that the battery be replaced. The SNAPHAT top may be replaced while VCC is applied to the device. Battery monitoring is a useful technique only when performed periodically. The M48T59/Y/V only monitors the battery when a nominal VCC is applied to the device. Thus applications which require extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique.
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This will cause the clock to lose time during the interval the battery/crystal is removed.
Note:
18/32
M48T59, M48T59Y, M48T59V
Clock operations
3.10
Century bit
Bit D5 and D4 of Clock Register 1FFCh contain the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle.
Note:
The WRITE Bit must be set in order to write to the CENTURY Bit.
3.11
Initial power-on defaults
Upon application of power to the device, the following register bits are set to a '0' state: WDS; BMB0-BMB4; RB0-RB1; AFE; ABE; W; R; FT (see Table 7). Table 7. Default values
Condition Initial power-up (Battery attach for SNAPHAT)(2) Subsequent power-up / RESET(3) Power-down(4)
1. WDS, BMB0-BMB4, RBO, RB1. 2. State of other control bits undefined. 3. State of other control bits remains unchanged. 4. Assuming these bits set to '1' prior to power-down.
W 0 0 0
R 0 0 0
FT 0 0 0
AFE 0 0 1
ABE 0
Watchdog register(1)
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ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 F (as shown in Figure 12 on page 20) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount.
19/32
Clock operations Figure 12. Supply voltage protection
VCC VCC
M48T59, M48T59Y, M48T59V
0.1F
DEVICE
VSS
AI02169
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M48T59, M48T59Y, M48T59V
Maximum ratings
4
Maximum ratings
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 8.
Symbol TA TSTG VIO VCC IO PD
Absolute maximum ratings
Parameter Ambient operating temperature Storage temperature (VCC off, oscillator off) Input or output voltages Supply voltage Output current Power dissipation M48T59/M48T59Y M48T59V Value 0 to 70 -40 to 85 260 -0.3 to 7 -0.3 to 7 Unit C C C
TSLD(1)(2)(3) Lead solder temperature for 10 seconds
1. For DIP package: Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds). 2. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225C (total thermal budget not to exceed 180C for between 90 to 150 seconds). 3. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260C (total thermal budget not to exceed 245C for greater than 30 seconds).
Caution: Caution:
Negative undershoots below -0.3 V are not allowed on any pin while in the Battery Back-up mode. Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
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21/32
DC and AC parameters
M48T59, M48T59Y, M48T59V
5
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measurement Conditions listed in Table 9. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 9. Operating and AC measurement conditions
Parameter Supply voltage (VCC) Ambient operating temperature (TA) Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing ref. voltages M48T59 4.75 to 5.5 0 to 70 100 5 0 to 3 1.5 M48T59Y 4.5 to 5.5 0 to 70 100 5 0 to 3 1.5 M48T59V 3.0 to 3.6 0 to 70 50 5 0 to 3 1.5 Unit V C pF ns
Note:
Output Hi-Z is defined as the point where data is no longer driven. Figure 13. AC measurement load circuit
DEVICE UNDER TEST
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(1) CL = 100pF
1.75V
CL includes JIG capacitance
AI02325
Excluding open-drain output pins Capacitance
Parameters(1)(2) Input capacitance Input / output capacitance Min Max 10 10 Unit pF pF
Table 10.
Symbol CIO(3)
1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested. 2. At 25C, f = 1 MHz. 3. Outputs deselected.
22/32
M48T59, M48T59Y, M48T59V Table 11.
Symbol ILI ILO(2) ICC ICC1 ICC2 VIL VIH VOL VOH
DC and AC parameters
DC characteristics
Parameter Input leakage current Output leakage current Supply current Supply current (standby) TTL Supply current (standby) CMOS Input low voltage Input high voltage Output low voltage Output low voltage (IRQ/FT and RST)(3) Output high voltage IOL = 2.1 mA IOL = 10 mA IOH = -1 mA 2.4 Test condition(1) 0V VIN VCC 0V VOUT VCC Outputs open E = VIH E = VCC - 0.2 V -0.3 2.2 M48T59/Y Min Max 1 1 50 3 3 0.8 VCC + 0.3 0.4 0.4 2.4 -0.3 2 M48T59V Unit Min Max 1 1 30 2 1 0.8 VCC + 0.3 0.4 0.4 A A mA mA mA V V V V V
1. Valid for ambient operating temperature: TA = 0 to 70C; VCC = 4.5 to 5.5 V, 4.75 to 5.5 V, or 3.0 to 3.6 V (except where noted). 2. Outputs deselected. 3. The IRQ/FT and RST pins are open drain.
Figure 14. Power down/up mode AC waveforms
VCC VPFD (max) VPFD (min) VSO tF tPD
RST
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RECOGNIZED
DON'T CARE
RECOGNIZED
HIGH-Z VALID
(PER CONTROL INPUT)
OUTPUTS
VALID
(PER CONTROL INPUT)
AI03258
23/32
DC and AC parameters Table 12.
Symbol tPD tF(2) tFB(3) tR tRB trec
M48T59, M48T59Y, M48T59V Power down/up AC characteristics
Parameter(1) Min 0 300 10 10 1 40 200 Max Unit s s s s s ms
E or W at VIH before power down VPFD (max) to VPFD (min) VCC fall time VPFD (min) to VSS VCC fall time VPFD (min) to VPFD (max) VCC rise time VSS to VPFD (min) VCC rise time VPFD (max) to RST high
1. Valid for ambient operating temperature: TA = 0 to 70C; VCC = 4.5 to 5.5 V, 4.75 to 5.5 V, or 3.0 to 3.6 V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200s after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 13.
Symbol VPFD
Power down/up trip points DC characteristics
Parameter(1)(2) M48T59 Power-fail deselect voltage Battery back-up switchover voltage Expected data retention time M48T59Y M48T59V M48T59/Y M48T59V 7 Min 4.5 4.2 2.7 Typ 4.6 4.35 2.9 3.0 Max 4.75 4.5 3.0 Unit
VSO tDR(3)
1. Valid for ambient operating temperature: TA = 0 to 70C; VCC = 4.5 to 5.5 V, 4.75 to 5.5 V, or 3.0 to 3.6 V (except where noted). 2. All voltages referenced to VSS. 3. At 25C, VCC = 0 V.
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24/32
M48T59, M48T59Y, M48T59V
Package mechanical data
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 15. PCDIP28 - 28-pin plastic DIP, battery CAPHAT, package outline
A2
A
A1 B1 B e3 D
N
L eA
C
e1
E
1
Note:
Drawing is not to scale. Table 14.
Symb
PCDIP28 - 28-pin plastic DIP, battery CAPHAT, package mechanical data
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Typ
t(s
mm Min
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Max 9.65 0.76 8.89 0.53 1.78 0.31
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PCDIP
inches Min 0.350 0.015 0.330 0.015 0.045 0.008 1.550 0.702 0.090 1.170 0.600 0.120 28 Max 0.380 0.030 0.350 0.021 0.070 0.012 1.570 0.722 0.110 1.430 0.630 0.150
8.89 0.38 8.38 0.38 1.14 0.20 39.37 17.83 2.29 29.72 15.24 3.05 28
39.88 18.34 2.79 36.32 16.00 3.81
25/32
Package mechanical data
M48T59, M48T59Y, M48T59V
Figure 16. SOH28 - 28-lead plastic small outline, battery SNAPHAT, package outline
A2 B e
A C eB CP
D
N
E
H A1 L
1 SOH-A
Note:
Drawing is not to scale. Table 15.
Symb Typ A A1 A2 B C D E e 0.05 2.34 0.36 0.15 Min Max 3.05 0.36 Typ
SOH28 - 28-lead plastic small outline, battery SNAPHAT, pack. mech. data
mm inches Min
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1.27 - 0 28
17.71 8.23
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2.69 0.51 0.32 8.89 - 3.61
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0.002 0.092 0.014 0.006 0.697 0.324
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Max 0.120 0.014 0.106 0.020 0.012 0.728 0.350 - 0.142 0.500 0.050 8
18.49
0.050
- 0.126 0.453 0.016 0 28
3.20
11.51 0.41
12.70 1.27 8
0.10
0.004
26/32
M48T59, M48T59Y, M48T59V
Package mechanical data
Figure 17. SH - 4-pin SNAPHAT housing for 48mAh battery & crystal, package outline
A1
A2 A A3
eA D
B eB
L
E
SHTK-A
Note:
Drawing is not to scale. Table 16.
SH - 4-pin SNAPHAT housing for 48mAh battery & crystal, package mech. data
mm
Symb Typ A A1 A2 A3 B D 6.73 6.48 Min Max 9.78 7.24
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Typ
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Max 0.385 0.285 0.275 0.015
0.38 0.56 0.018 0.835 0.560 0.612 0.126 0.080
0.46
0.022 0.860 0.590 0.628 0.142 0.090
21.21
21.84 14.99 15.95 3.61 2.29
14.22 15.55 3.20 2.03
27/32
Package mechanical data
M48T59, M48T59Y, M48T59V
Figure 18. SH - 4-pin SNAPHAT housing for 120mAh battery & crystal, package outline
A1
A2 A A3
eA D
B eB
L
E
SHTK-A
Note:
Drawing is not to scale. Table 17.
SH - 4-pin SNAPHAT housing for 120mAh battery & crystal, package mech. data
mm
Symb Typ A A1 A2 A3 B D E 8.00 7.24 Min Max 10.54 8.51 8.00
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inches Min 0.315 0.285
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Max 0.415 0.335 0.315 0.015
0.018 0.835 0.680 0.612 0.126 0.080
0.022 0.860 0.710 0.628 0.142 0.090
21.84
17.27 15.55 3.20
18.03 15.95
2.03
28/32
M48T59, M48T59Y, M48T59V
Part numbering
7
Part numbering
Table 18.
Example: Device type M48T Supply voltage and write protect voltage 59(1) = VCC = 4.75 to 5.5 V; VPFD = 4.5 to 4.75 V 59Y = VCC = 4.5 to 5.5 V; VPFD = 4.2 to 4.5 V 59V(2) = VCC = 3.0 to 3.6 V; VPFD = 2.7 to 3.0 V Speed -70 = 70 ns Package PC = PCDIP28 MH(3) = SOH28 Temperature range 1 = 0 to 70C Shipping method For SOH28:
Ordering information scheme
M48T 59Y -70 MH 1 E
E = Lead-free package (ECOPACK(R)), tubes F = Lead-free package (ECOPACK(R)), tape & reel For PCDIP28: blank = tubes
1. The M48T59 part is offered with the PCDIP28 (e.g., CAPHATTM) package only.
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2. Contact local ST sales office for availability of 3.3 V version. 3. The SOIC package (SOH28) requires the SNAPHAT(R) battery/crystal package which is ordered separately under the part number "M4TXX-BR12SH" in plastic tube or "M4TXX-BR12SHTR" in tape & reel form (see Table 19).
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Do not place the SNAPHAT battery package "M4TXX-BR12SH" in conductive foam as it will drain the lithium button-cell battery. For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you.
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Part numbering Table 19. SNAPHAT battery table
Description Lithium battery (48mAh) SNAPHAT Lithium battery (120mAh) SNAPHAT
M48T59, M48T59Y, M48T59V
Part number M4T28-BR12SH1 M4T32-BR12SHx
Package SH SH
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M48T59, M48T59Y, M48T59V
Revision history
8
Revision history
Table 20.
Date Oct-1999 22-Mar-2000 13-Jul-2000 14-May-2001 31-Jul-2001 06-Aug-2001 20-May-2002 07-Aug-2002 01-Apr-2003 02-Apr-2004 25-Nov-2004
Document revision history
Revision 1.0 1.1 2.0 3.0 3.1 3.2 3.3 3.4 4.0 5.0 6.0 First Issue Century Bit Paragraph added; tFB value changed (Table 12) From Preliminary Data to Data Sheet Reformatted, Ind. Temp. added (Table 9), SNAPHAT table added (Table 19), temp/voltage info. added to tables (Table 10, 11, 3, 4, 12, 13) Formatting changes from recent document review findings Fix text for Setting the Alarm Clock (Figure 10) Modify reflow time and temperature footnotes (Table 8) Add marketing status note (Table 18) v2.2 template applied; test condition updated (Table 13) Changes
Reformatted; update Lead-free package information (Table 8, 18)
Remove all Industrial temperature references (Table 3, 4, 8, 9, 11, 12, 13, 18) Product status is "Not for New Design"; reformatted document; added lead-free second level interconnect information to cover page and Section 6: Package mechanical data; updated Table 11, 19.
01-Apr-2008
7.0
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M48T59, M48T59Y, M48T59V
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